MCRC Test Bench Diagram for The Counter Paper Question

1. In this question you are to implement the following truth table (where – represents a don’tcare value) using the requested commands/styles in Verilog. Simulate each case using yourtestbench and then synthesize each version and submit the screen capture of the RTL view.a b c y0 0 0 10 0 1 10 1 0 -0 1 1 -1 0 0 01 0 1 01 1 0 11 1 1 0Figure 1. Truth table for Question 1a) Using concurrent continuous assignment(s)b) Using behavioral code with case statement

c) Using behavioral code with if statement

d) Using structural code (implement the SUM-OF-PRODUCT representation of thecircuit using primitive gates of AND, OR, and NOT.e) Using reduction operators 2. In this question, you are asked to design a synthesizable ALU using the requestedcommands/styles in Verilog. This ALU gets two 8-bit inputs (A, B) and a 4-bit select input(S) based on which decides about the operation that should be executed (output Q is 8-bit).What follows shows these operations:If S=0 => Addition (i.e., A+B)

If S=1 => Subtraction (A-B)

If S=2 => Multiplication (only the least 8 significant bits are shown in output)2If S=3 => Shift A to the left B times (and add 0 from right side)

If S=4 => Rotate A to the right B times

If S=5 => A is ANDed with BIf S=6 => A is ORded with BIf S=7 => A is XORed with BIf S=8 => A is NANDed with B

If S=9 => Complement of A is computed

Design this ALU using the following code styles:

a) Using concurrent continuous assignment(s)b) Using behavioral code with case statement

c) Using behavioral code with if statement

3. Reconsider question 2 with the assumption that the output is a registered output, i.e., Q isloaded by the rising edge of the clock signal when reset is not active (RESET=0). For thiscase consider a synchronous resetting mechanism (RESET only acts in the rising edgeof the CLK signal). Implement the circuit with the following styles:

a) Using behavioral code with case statement

b) Using behavioral code with if statement

4. Leveraging the concatenation operator, create a module that accepts a 64-bit input X, andswaps pairs of even-and odd bytes to produce a 64-bit output U. The output should beregistered using a clock signal CLK.5.a) Design a 4-bit counter with inputs/outputs shown in Fig. 2. It should be a synchronouscounter with asynchronous resetting mechanism and work as follows:● If ENABLE=’0’, the output keeps its previous value regardless of other input values.● If ENABLE=’1’ and LOAD=’1’, the 4-bit input value (V) is loaded into the counterwith the rising edge of the CLK signal regardless of other input values. ● If ENABLE=’1’ and LOAD=’0’, then it counts synchronously up or down withrising edge of CLK based on the value of UP (if this value is ‘1’ it counts up,otherwise it counts down).● The RCO output becomes ‘1’ only in the following cases:⮚ when ENABLE=’1’ and UP=’1’ and Q=’1111’ ⮚ when ENABLE=’1’ and UP=’0’ and Q=’0000’3 Note that all cases above occurs only if CLEAR=’0”. However, if CLEAR=’1’, bothQ and RCO will be reset immediately (asynchronous resetting mechanism)

Figure 2. Diagram for the Counter in Question 5

b) Write a testbench for your circuit that does the following:-First it loads the value of 10 (decimal) in the counter, then starts counting down for 6 clockcycles. After that it counts up for 20 clock cycles. c) Implement an 8-bit counter with the same specification using 2 samples of the circuitdesigned in part a. In this circuit RCO signal becomes ‘1’ in following cases

⮚ when ENABLE=’1’ and UP=’1’ and Q=’11111111’

⮚ when ENABLE=’1’ and UP=’0’ and Q=’00000000’d) Write a testbench for your 8-bit counter that does the following:-First it loads the value of 122 (decimal) in the counter, then starts counting down for 124clock cycles. 1. In this question you are to implement the following truth table (where – represents a don’t
care value) using the requested commands/styles in Verilog. Simulate each case using your
testbench and then synthesize each version and submit the screen capture of the RTL view.
a b c
y
0 0 0 1
0 0 1 1
0 1 0
–
0 1 1
–
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0

Figure 1. Truth table for Question 1

a)
b)
c)
d)
Using concurrent continuous assignment(s)
Using behavioral code with case statement
Using behavioral code with if statement
Using structural code (implement the SUM-OF-PRODUCT representation of the
circuit using primitive gates of AND, OR, and NOT.
e) Using reduction operators

2. In this question, you are asked to design a synthesizable ALU using the requested
commands/styles in Verilog. This ALU gets two 8-bit inputs (A, B) and a 4-bit select input
(S) based on which decides about the operation that should be executed (output Q is 8-bit).
What follows shows these operations

:
If S=0 => Addition (i.e., A+B)
If S=1 => Subtraction (A-B)
If S=2 => Multiplication (only the least 8 significant bits are shown in output)
If S=3 => Shift A to the left B times (and add 0 from right side)
1
If S=4 => Rotate A to the right B times

If S=5 => A is ANDed with B

If S=6 => A is ORded with B

If S=7 => A is XORed with B

If S=8 => A is NANDed with B
If S=9 => Complement of A is computed
Design this ALU using the following code styles:

a) Using concurrent continuous assignment(s)

b) Using behavioral code with case statement
c) Using behavioral code with if statement
3. Reconsider question 2 with the assumption that the output is a registered output, i.e., Q is
loaded by the rising edge of the clock signal when reset is not active (RESET=0). For this
case consider a synchronous resetting mechanism (RESET only acts in the rising edge
of the CLK signal). Implement the circuit with the following styles:
a) Using behavioral code with case statement
b) Using behavioral code with if statement

4. Leveraging the concatenation operator, create a module that accepts a 64-bit input X, and
swaps pairs of even-and odd bytes to produce a 64-bit output U. The output should be
registered using a clock signal CLK.

5.
a) Design a 4-bit counter with inputs/outputs shown in Fig. 2. It should be a synchronous
counter with asynchronous resetting mechanism and work as follows:

● If ENABLE=’0’, the output keeps its previous value regardless of other input
values.
● If ENABLE=’1’ and LOAD=’1’, the 4-bit input value (V) is loaded into the
counter with the rising edge of the CLK signal regardless of other input values.

● If ENABLE=’1’ and LOAD=’0’, then it counts synchronously up or down with
rising edge of CLK based on the value of UP (if this value is ‘1’ it counts up,
otherwise it counts down).

2

● The RCO output becomes ‘1’ only in the following cases:

⮚ when ENABLE=’1’ and UP=’1’ and Q=’1111’
⮚ when ENABLE=’1’ and UP=’0’ and Q=’0000’
Note that all cases above occurs only if CLEAR=’0”. However, if CLEAR=’1’, both
Q and RCO will be reset immediately (asynchronous resetting mechanism)
Figure 2. Diagram for the Counter in Question 5
b) Write a testbench for your circuit that does the following:
-First it loads the value of 10 (decimal) in the counter, then starts counting down for 6 clock
cycles. After that it counts up for 20 clock cycles.
c) Implement an 8-bit counter with the same specification using 2 samples of the circuit
designed in part a. In this circuit RCO signal becomes ‘1’ in following cases
⮚ when ENABLE=’1’ and UP=’1’ and Q=’11111111’

⮚ when ENABLE=’1’ and UP=’0’ and Q=’00000000’

d) Write a testbench for your 8-bit counter that does the following:
-First it loads the value of 122 (decimal) in the counter, then starts counting down for 124
clock cycles.
3