Machine Learning

Read chapter and answer the questions

Assembly Language for x86 Processors
Eighth Edition
Chapter 2
x86 Processor Architecture
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2-1
Chapter Overview
• General Concepts
• IA-32 Processor Architecture
• IA-32 Memory Management
• 64-bit Processors
• Components of an IA-32 Microcomputer
• Input-Output System
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2-2
General Concepts
• Basic microcomputer design
• Instruction execution cycle
• Reading from memory
• How programs run
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2-3
Basic Microcomputer Design
• clock synchronizes CPU operations
• control unit (CU) coordinates sequence of
execution steps
• ALU performs arithmetic and bitwise processing
data bus
registers
Central Processor Unit
(CPU)
ALU
CU
Memory Storage
Unit
I/O
Device
#1
I/O
Device
#2
clock
control bus
address bus
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2-4
Clock
• synchronizes all CPU and BUS operations
• machine (clock) cycle measures time of a single
operation
• clock is used to trigger events
one cycle
1
0
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2-5
Irvine, Kip R. Assembly Language
for x86 Processors 7/e, 2015.
Clock
• Timing waveforms example
• A CPU operating at 50MHz (one clock cycle = 20ns)
• A memory chip is designed with an access speed not to
exceed 50ns
• Each memory request will require at least two-and-a
half CPU clock cycles (50ns/20ns = 2.5 clock cycles)
6
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2-6
Irvine, Kip R. Assembly Language
for x86 Processors 7/e, 2015.
Clock
• Each memory request will require at least two-and-a half CPU clock
cycles (50ns/20ns = 2.5 clock cycles)
7
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2-7
What’s Next (1 of 5)
• General Concepts
• IA-32 Processor Architecture
• IA-32 Memory Management
• 64-Bit Processors
• Components of an IA-32 Microcomputer
• Input-Output System
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2-8
Instruction Execution Cycle
• Fetch
• Decode
• Fetch operands
• Execute
• Store output
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2-9
Irvine, Kip R. Assembly Language
for x86 Processors 7/e, 2015.
Instruction Execution Cycle
• Typically simplified to:
– Fetch
– Decode
– Execute
10
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 10
Reading from Memory
Multiple machine cycles are required when reading from
memory, because it responds much more slowly than the
CPU. The steps are:
1. Place the address of the value you want to read on the address
bus.
2. Assert (changing the value of) the processor’s RD (read) pin.
3. Wait one clock cycle for the memory chips to respond.
4. Copy the data from the data bus into the destination operand
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 11
Cache Memory
• High-speed expensive static RAM both inside and
outside the CPU.
– Level-1 cache: inside the CPU
– Level-2 cache: outside the CPU
• Cache hit: when data to be read is already in
cache memory
• Cache miss: when data to be read is not in cache
memory.
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 12
How a Program Runs
• Program loaded into
memory by program
loader
• The OS then points
to the program entry
point
User
sends program
name to
Operating
system
gets starting
cluster from
searches for
program in
returns to
System
path
loads and
starts
Directory
entry
Current
directory
Program
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 13
IA-32 Processor Architecture
• Modes of operation
• Basic execution environment
• Floating-point unit
• Intel Microprocessor history
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 14
Modes of Operation
• Protected mode
– native mode (Windows, Linux)
• Real-address mode
– native MS-DOS
• System management mode
– power management, system security, diagnostics
• Virtual-8086 mode
− hybrid of Protected
− each program has its own 8086 computer
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 15
Basic Execution Environment
• Addressable memory
• General-purpose registers
• Index and base registers
• Specialized register uses
• Status flags
• Floating-point, MMX, XMM registers
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 16
Addressable Memory
• Protected mode
– 4 GB
– 32-bit address
• Real-address and Virtual-8086 modes
– 1 MB space
– 20-bit address
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 17
General-Purpose Registers
Named storage locations inside the CPU, optimized
for speed.
32-bit General-Purpose Registers
EAX
EBP
EBX
ESP
ECX
ESI
EDX
EDI
16-bit Segment Registers
EFLAGS
EIP
CS
ES
SS
FS
DS
GS
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 18
Accessing Parts of Registers
• Use 8-bit name,16-bit name, or 32-bit name
• Applies to EAX, EBX, ECX, and EDX
8
8
AH
AL
AX
EAX
8 bits + 8 bits
16 bits
32 bits
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 19
Index and Base Registers
• Some registers have only a 16-bit name for their
lower half:
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 20
Irvine, Kip R. Assembly Language
for x86 Processors 7/e, 2015.
Some Specialized Register Uses (1 of 3)
• General-Purpose
– EAX – (extended) accumulator
 multiplication & division
– ECX – loop counter
– ESP – (extended) stack pointer
 addresses data on the stack
– ESI, EDI – index registers
 extended source and extended destination
– EBP – extended frame pointer (stack)
 used by high-level languages to reference function
parameters and local variables on the stack
21
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 21
Irvine, Kip R. Assembly Language
for x86 Processors 7/e, 2015.
Some Specialized Register Uses (2 of 3)
• Segment
– Indicate base addresses of preassigned memory
areas (segments)
 CS – code segment
 DS – data segment
 SS – stack segment
 ES, FS, GS – additional segments
– ES (extra segment), FS and GS, provide
additional segments for storing data.
22
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 22
Irvine, Kip R. Assembly Language
for x86 Processors 7/e, 2015.
Some Specialized Register Uses (3 of 3)
• EIP – instruction pointer
– register contains the address of the next
instruction to execute
• EFLAGS (execution flags) or just
FLAGS
– status and control flags
– each flag is a single binary bit
Status FLAGS: Next Slide
23
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 23
Status Flags
• Carry
– unsigned arithmetic out of range
• Overflow
– signed arithmetic out of range
• Sign
– result is negative
• Zero
– result is zero
• Auxiliary Carry
– carry from bit 3 to bit 4
• Parity
– sum of 1 bits is an even number
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 24
Floating-Point, MMX, XMM Registers
• Eight 80-bit floating-point data
registers
– ST(0), ST(1), . . . , ST(7)
– arranged in a stack
– used for all floating-point arithmetic
80-bit Data Registers
ST(0)
ST(1)
ST(2)
ST(3)
• Eight 64-bit MMX registers
ST(4)
• Eight 128-bit XMM registers for singleinstruction multiple-data (SIMD)
operations
ST(5)
ST(6)
ST(7)
SIMD – Single Instruction, Multiple Data
Opcode Register
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 25
What’s Next (2 of 5)
• General Concepts
• IA-32 Processor Architecture
• IA-32 Memory Management
• 64-Bit Processors
• Components of an IA-32 Microcomputer
• Input-Output System
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 26
IA-32 Memory Management
• Real-address mode
• Calculating linear addresses
• Protected mode
• Multi-segment model
• Paging
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 27
Irvine, Kip R. Assembly Language
for x86 Processors 7/e, 2015.
Real Address Mode
• 1 MB addressable RAM
– (00000 to FFFFFh)
• The processor can run only one program at a time
• Applications can access any memory location
• MS-DOS runs in Real Address Mode
28
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 28
Protected Mode
• 4 GB addressable RAM
– (00000000 to FFFFFFFFh)
• Each program assigned a memory partition of 4 GB which
is protected from other programs
• Designed for multitasking
• Supported by Linux & MS-Windows
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 29
What’s Next (4 of 5)
• General Concepts
• IA-32 Processor Architecture
• IA-32 Memory Management
• 64-Bit Processors
• Components of an IA-32 Microcomputer
• Input-Output System
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 33
Components of an IA-32 Microcomputer
• Motherboard
• Video output
• Memory
• Input-output ports
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 34
Motherboard
• CPU socket
• External cache memory slots
• Main memory slots
• BIOS chips
• Sound synthesizer chip (optional)
• Video controller chip (optional)
• IDE, parallel, serial, USB, video, keyboard, joystick,
network, and mouse connectors
• PCI bus connectors (expansion cards)
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 35
Intel D850MD Motherboard
Video
Audio
chip
PCI slots
AGP slot
Firmware
hub
mouse, keyboard,
parallel, serial, and
USB connectors
memory controller hub
Pentium 4
socket
dynamic
RAM
Speaker
Power
connector
Diskette connector
Source: Intel® Desktop Board D850MD/D850MV IDE drive connectors
Technical Product Specification
Battery
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 36
Memory (1 of 2)
• ROM
– read-only memory
• EPROM
– erasable programmable read-only memory
• Dynamic RAM (DRAM)
– inexpensive; must be refreshed constantly
• Static RAM (SRAM)
– expensive; used for cache memory; no refresh required
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 40
Memory (2 of 2)
• Video RAM (VRAM)
– dual ported; optimized for constant video refresh
• CMOS RAM
– complimentary metal-oxide semiconductor
– system setup information
• See: Intel platform memory (Intel technology brief:
link address may change)
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 41
Input-Output Ports
• USB (universal serial bus)
– intelligent high-speed connection to devices
– up to 12 megabits/second
– USB hub connects multiple devices
– enumeration: computer queries devices
– supports hot connections
• Parallel
– short cable, high speed
– common for printers
– bidirectional, parallel data transfer
– Intel 8255 controller chip
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 42
Input-Output Ports (cont)
• Serial
– RS-232 serial port
– one bit at a time
– uses long cables and modems
– 16550 UART (universal asynchronous receiver
transmitter)
– programmable in assembly language
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 43
Device Interfaces
• ATA host adapters
– intelligent drive electronics (hard drive, CDROM)
• SATA (Serial ATA)
– inexpensive, fast, bidirectional
• FireWire
– high speed (800 MB/sec), many devices at once
• Bluetooth
– small amounts of data, short distances, low power usage
• Wi-Fi (wireless Ethernet)
– IEEE 802.11 standard, faster than Bluetooth
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 44
What’s Next (5 of 5)
• General Concepts
• IA-32 Processor Architecture
• IA-32 Memory Management
• Components of an IA-32 Microcomputer
• Input-Output System
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 45
Levels of Input-Output
• Level 3: High-level language function
– examples: C++, Java
– portable, convenient, not always the fastest
• Level 2: Operating system
– Application Programming Interface (API)
– extended capabilities, lots of details to master
• Level 1: BIOS
– drivers that communicate directly with devices
– OS security may prevent application-level code from working at
this level
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 46
Displaying a String of Characters
When a HLL program displays a string of characters, the
following steps take place:
Application Program
Level 3
OS Function
Level 2
BIOS Function
Level 1
Hardware
Level 0
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 47
Programming levels
Assembly language programs can perform inputoutput at each of the following levels:
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 48
Summary
• Central Processing Unit (CPU)
• Arithmetic Logic Unit (ALU)
• Instruction execution cycle
• Multitasking
• Floating Point Unit (FPU)
• Complex Instruction Set
• Real mode and Protected mode
• Motherboard components
• Memory types
• Input/Output and access levels
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 49
42 69 6E 61 72 79
What does this say?
Binary
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 50
Copyright
This work is protected by United States copyright laws and is
provided solely for the use of instructors in teaching their
courses and assessing student learning. Dissemination or sale of
any part of this work (including on the World Wide Web) will
destroy the integrity of the work and is not permitted. The work
and materials from it should never be made available to students
except by instructors using the accompanying text in their
classes. All recipients of this work are expected to abide by these
restrictions and to honor the intended pedagogical purposes and
the needs of other instructors who rely on these materials.
Copyright © 2020, 2015, 2011 Pearson Education, Inc. All Rights Reserved
2 – 51