everything on PDF

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CSE/EEE 230 – Assignment 7
Important: This is an individual assignment. Please do not collaborate.
Make sure to follow the academic integrity policies. Using work done by someone else will be
considered a violation of the academic integrity and will result in a report to the Dean’s office.
Your work should not match with anything found online.
Copying any part of this assignment, and providing them to another person or posting them on
the Internet without a permission of the instructor will be a violation of its copyright.
http://www.asu.edu/copyright/
No late submissions will be accepted.
Show all the steps to receive full credit.
There are 3 questions. The score will be scaled down to a total of 3 points.
Make sure to segment your document for the 3 questions.
The following MIPS Code is executed using the multi cycle MIPS architecture.
Start:
Loop:
addiu $t9, $0, 230
addi $t8, $0, 4
add $s1, $s0, $t8
slt $t0, $s0, $s1
beq $t0, $0, Exit
lbu $t1, 0($s0)
sub $t1, $t1, $t9
sb $t1, 0($s0)
addi $s0, $s0, 1
j Loop
Exit:
Question 1: Multi-cycle Implementation – For the above code, write the execution steps (which
of the 5 steps and in what order) and the corresponding control signals and values during each
step. (15 points)
Question 2: Execution Time – For the above code, compute the execution time for each
instruction and for the complete code for multi-cycle implementation. (5 points)
(i) Given the following access times for the critical functional units, compute the time taken to
execute each instruction. You may group the instructions with the same execution time.
Memory Access = 0.26ns;
Register Access = 0.1ns;
ALU execution = 0.2ns
(ii) Assuming all instructions are executed using a fixed clock cycle length. What is the execution time
for the complete code/program using multi-cycle implementation?
The following MIPS Code is executed using the MIPS pipeline architecture. Include all iterations
of the loop.
Start:
Loop:
Exit:
addiu $s1, $0, 0x1234
addi $s0, $0, 0x122C
lb $t1, 0($s0)
sb $t1, 2($s0)
nor $t2, $t1, $t1
sb $t2, 0($s0)
addi $s0, $s0, 4
bne $s0, $s1, Loop
addi $s0, $0, 0x122C
Question 3: Pipeline – For the above code, write the Pipeline Implementation by resolving all the
three hazards. (10 points). Consider the following assumptions: (structural, data and control
hazards are resolved using hardware)
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There is separate instruction and data memory access.
Register read and write can happen within the same clock cycle.
There is Forwarding unit. Show data forwarding between the correct stages, wherever
necessary.
There is only Hazard detection Unit, i.e., resolution for control hazards only using hazard
detection unit and no branch prediction.
Use stall if an instruction is delayed after fetch.
Use nop if an instruction is delayed before fetch.