Digital system design question

I need help please solving these questions from an old exam

The course is digital system design

We’re dealing with verilog and vhdl in this course

And we are working on modelsim applicatio

EE 421 – Digital Systems Design
Fall 2017
Final Exam
December 14, 2017
(e) (20 points) Write a test bench to exercise the design. Your test bench should include four Vetilong
tasks as described in Table 1. Each task should accept inputs which denote (1) the womber of
clock cycles before the front of the train passes the second sensor, (2) the number of clock cydes
before the end of the train passes the first sensor, and (3) the number of clock cycles before the
end of the train passes the second sensor. Using these parameters, the sensors should be activated
appropriately. Submit a copy of your tasks and test bench source code along with simulation
waveforms that depict the desired behaviors.
Table 1: Verilog task descriptons
Task Name
task.e2w.long
task.e2w.short
Description
The train approaches from the cast and it
is more than 800 meters long,
The train approaches from the east and it
is less than 800 meters long
The train approaches from the west and
it is more than 800 meters long
The train approaches from the west and
it is less than 800 meters long
task.20.long
task w2e short
Problems
13. Consider a scenario in which a signal crosses in wynchronous bonudary. The frequency of the clock in
the receiving domain is 5x the frequency of the clock in the transmitting domain. You are to design
sampling circuit which will capture a falling edge on the sigut un producen cok-long logie HIGH
output pulse in the receiving domain. Asume that any state on the transitted signal will last nt
least one clock period in the receiving domain
w) (10 points) Draw the scheutic for your circuit brew
(b) (10 points) Write behavioral Verilog code which implements your design. Submit your printed
source code.
() (10 points) Create a test bench which shows the desired behavior of your circuit. Assume
your input consists of a single-clock-long positive-going pulse sent from the transmitting domain
Submit your test bench source code and a waveform showing both the input and the output.
EE621 – Didal System Delp
Fall 2017
Final Exam
Deoember 14, 2017
14. A train track (going out-est) Crotond (going north-south). Trains may approach the crossing
from the direction Sensors are placed 400 metersom either side of the crossing When an approaching
train pass the first sensor in its path, crowing gates are lowered to stop automobile trate on the
road. The wates remit lowered until the entire train paned the second sensor. Trains may be
short encaugh to fit entirely between the senses (triggering neither they The Fate controller
has two inputs (sensort and sensor2), and one output (gateDown).
(a) (10 points) Draw the state din gran for the crossing ante controller
(b) (10 points) Write RTL Verilog code (do not write structural code) which implements this design
Submit your printed source code.
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