computer architecture problems

I want the attached problems solved in 7 hours

2)Consider the pipelined implementation (without forwarding and/or stalling) of the MIPS microprocessor.

(a) Explain how this pipelined implementation deals with I-type conditional branch instructions in the case the

branch is not taken and in the case the branch is taken.

(b) Explain why data dependency hazards may occur in this implementation.

(c) List all possible instruction sequences that may exhibit data dependency hazards.

(d) For each sequence in (c), give a software equivalent that does not suffer from the data dependency limitation.

3)Identify all of the data dependencies in the following code. Which dependencies are data hazards that will be

resolved via forwarding?

add $2, $5, $4

add $5, $2, $4

sw $5, 100($2)

lw $4, 0($5)

add $3, $2, $4

4) Assume a 5 stage pipelined MIPS processor with stages IF, ID, EX, MEM and WB. LOAD and STORE are the only

instructions accessing memory. Branches are resolved at ID stage.

(a) Give a code sequence that has data hazard which can be solved by forwarding.

(b) Give a code sequence that has data hazard that cannot be solved by forwarding. Indicate stall cycles required.

(c) Explain branch hazards. Why do branch hazards degrade the performance?

5)Consider the following MIPS code sequence.

add $2, $2, $2

add $5, $5, $5

L: lw $8, 1000 ($5)

sub $5, $2, $8

addi $2, $2, -4

beq $2, $0, L

sw $5, 500 ($2)

Assume that there is no forwarding unit (including register file forwarding) but instead there is a data hazard

detection unit that introduces the stalls needed to avoid data hazards. Suppose the processor uses Assume Branch

Not Taken strategy and branches are resolved in the ID stage. Illustrate the execution of the given code.

6)Using the same sequence of instructions as in Problem 5, now suppose the situation beq will be taken and branches

are resolved in the ID stage (Processor uses Assume Branch Not Taken strategy). Show the execution of the given

code around the loop, starting with the execution of a beq instruction and ending with the next execution of a beq.

7) Using the same instruction sequence as in Problem 5, redraw a diagram that describes the execution of the given

code assuming that the processor has a forwarding unit.

8) An unpipelined processor has a cycle time of 30ns. What is the cycle time of a pipelined version of the processor

with 5 evenly divided pipeline stages if each pipeline latch has a latency of 1ns? What if the processor is divided

into 50 pipeline stages? What is the minimum cycle time we can hope to get if we could add as many pipeline stages

as desired?

Consider the following code segment within a loop body:

if ( n % 2 == 0 ) // branch 1

a++;

if ( n % 10 == 0 ) // branch 2

b++;

Assume that the following list of 10 values of n is to be processed by 10 iterations of this loop:

18, 29, 30, 41, 52, 60, 79, 80, 91, 100

List the predictions for the following branch prediction schemes and calculate the prediction accuracies

for each scheme.

(a) Always taken.

(b) Always not taken.

(a) 1-bit predictor, initialized to predict taken.

(b) 2-bit predictor, initialized to weakly predict taken.

10) Consider a processor with a delayed branch that has three delay slots. Three compilers compiler A, compiler B and

compiler C, could run on this processor. Compiler A can fill the first delay slot 60% of the time and the second

delay slot 40% of the time and the third delay slot 20% of the time (filling delay slot is independent). Compiler B

can fully fill all the three delay slots. Compiler C leaves all the slots empty. Assuming that branches account for

20% of all instructions and arithmetic/logic operations for the remaining 80% of the instructions for any program,

what is the improvement of CPI with compiler B compared to CPI with compiler A and compared to CPI with

compiler C? Assume that CPI of arithmetic/logic operations is 1.