Computer Architecture and Organization

TheUniversity of Toledo

Electrical Engineering and Computer Science

EECS 2110 – Computer Architecture and Organization

Homework Assignment #4 –MIPS Assembly & Machine Language

Instructions

This homework is an individual activity. You may discuss the problem statements with others
to understand in clear terms what the problem requires. The solution however must be your
own work!

All problems (questions or exercises) and indicated subparts must be solved for full credit.
Problems or their subparts are not necessarily equally weighted. Not all problems may be
graded for correctness.

You must include solution steps in reasonable detail to document the process of developing the
answer. Simply providing an answer without demonstrating the solution path may not receive
any credit.

Use one side of a letter-size typing paper and staple the submission package on the top left.
Presentation, organization, neatness and legibility of the submission will be considered for

grading. Computer use for solution document preparation is not required. You may write and
draw by hand.

Include the following on the top right of the first page: Your full name, rocket number, course
number & name, homework #, and the date of submission. Initialize every other sheet.

Submit as hardcopy only: electronic submission is not permitted unless preauthorized by the
instructor for a valid reason.

Late submission is subject to penalty!

Questions

1) Consider the two binary numbers given below:

0010 0100 1001 0010 0100 1001 0010 01002
1000 0000 0000 1111 0000 1111 0101 00002

a. What base 10 number does each binary number represent, assuming that it is an unsigned

integer? Show the conversion process.
b. What base 10 number does each binary number represent, assuming that it is a two’s

complement integer? Show the conversion process.
c. What hexadecimal number does each binary number represent? Show the conversion process.

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2) Consider the two base 10 numbers given below:
-1
1024

a. Convert each decimal number to 2’s complement binary using
I. 8 bits,

II. 16 bits and
III. 32 bits.

b. Represent each binary number in part a in hexadecimal.

3) Registers $s0 and $s1 hold the values as shown in the table below. You will be asked to consider

execution of MIPS assembly language instruction(s) which will use these two registers and analyze
the result. Note that there are two cases as part a and part b in the below table.

a. $s0 = 0x80000000, $s1 = 0xD0000000
b. $s0 = 0x00000001, $s1 = 0xFFFFFFFF

a. For the contents of registers $s0 and $s1 as specified above, what is the value of $t0 following

the execution of instruction below? Is the result in $t0 correct, or has there been overflow?
Explain.

add $t0, $s0, $s1
b. For the contents of registers $s0 and $s1 as specified above, what is the value of $t0 following

the execution of the assembly instruction below? Is the result in $t0 correct, or has there been
overflow? Explain.

sub $t0, $s0, $s1
c. For the contents of registers $s0 and $s1 as specified above, what is the value of $t0 following

the execution of the assembly code with two back-to-back instructions below? Is the result in
$t0 correct , or has there been overflow? Explain.

add $t0, $s0, $s1
add $t0, $t0, $s0

4) In the following table, each row in the data table contains the values of various fields of a single
MIPS instruction.

a. op=0, rs=3, rt=2, rd=3, shamt=0, funct=34
b. op=0x23, rs=1, rt=2, const=0x4

a. What type (I-type, R-type, or J-type) instruction do the instructions above represent? Explain.
b. What is the binary representation of the instructions above? Show the construction process

ofor the machine language encoding.
c. What are the MIPS assembly instructions (in symbolic form) described above?

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5) Consider the machine language encoding of instructions (in binary) given below.

a. 0000 0010 0001 0000 1000 0000 0010 0000
b. 0000 0001 0100 1011 0100 1000 0010 0010

a. What type (I-type, R-type, J-type) instruction do the binary entries above represent? Explain

your reasoning.
b. For the binary entries above, what instruction do they represent? Show the analysis process

that leads to a specific instruction in assembly or symbolic form.

6) Consider the MIPS instructions below.

a. addi $t0, $t0, 0
b. sw $t1, 32($t2)

a. What type (I-type, R-type, J-type) instruction do the instructions above represent?
b. For the instructions above, show the binary then hexadecimal representation of these

instructions. You must show how you determine each subfield value in the machine encoding
of each instruction.

7) Consider the values stored in indicated registers in the below table.

a. $t0 = 0xAAAAAAAA, $t1 = 0x12345678
b. $t0 = 0xF00DD00D, $t1 = 0x11111111

a. What is the value of $t2 for the following sequence of instructions? Explain in detail for each

instruction.
sll $t2, $t0, 44
or $t2, $t2, $t1

b. What is the value of $t2 for the following sequence of instructions? Explain in detail for each
instruction.

sll $t2, $t0, 4
andi $t2, $t2, –1

c. What is the value of $t2 for the following sequence of instructions? Explain in detail for each
instruction.

srl $t2, $t0, 3
andi $t2, $t2, 0xFFEF

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8) For these problems, the table holds various binary values for register $t0. Given the value of $t0, you
will be asked to evaluate the outcome of different branches.

a. 0010 0100 1001 0010 0100 1001 0010 0100
b. 0101 1111 1011 1110 0100 0000 0000 0000

a. Suppose that register $t0 contains a value from above and $t1 has the value 0011 1111 1111

1000 0000 0000 0000 0000. Note the result of executing these instructions on particular
registers. What is the value of $t2 after the following instructions? Explain.

slt $t2, $t0, $t1
beq $t2, $0, ELSE

j DONE
ELSE: addi $t2, $0, 2
DONE:

b. Suppose that register $t0 contains a value from the table above and is compared against the
value X, as used in the MIPS instruction below. Note the format of the slti instruction. For what
values of X, if any, will $t2 be equal to 1? Explain.

slti $t2, $t0, X
c. Suppose the program counter (PC) is set to 0x0000 0020.

i. Is it possible to use the jump MIPS assembly instruction to set the PC to the address as
shown in the data table above? Explain your reasoning.

ii. Is it possible to use the branch-on-equal MIPS assembly instruction to set the PC to the
address as shown in the data table above? Explain your reasoning.