ASU Engineering Design Lab Report

CMPE 315 LabLAB Assignment #3 for CMPE 315
Assigned: Thrs, Sep 23rd
Due: Mon, Oct 4th
Description: Create a compact layout and perform simulations for the following gates
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Draw the layout for a minimum sized inverter and size transistors according to the INVx1
schematic from lab2. Use the simulation and config views from the previous lab to run simulations to verify your layout. Perform simulations with four INVx1 cells connected as load
from the previous lab.
Draw the layout for the NAND2x1 and NOR2x1 cells from the previous lab again using same
transistor sizes as lab2. Run simulation with four INVx1 as load using the simulation and config views to verify their functionality.
Draw the schematic and layout for a 4 input OAI and 4 input AOI gates using instances of
INVx1, NAND2x1 and NOR2x1. Create schematic view and config views for simulation.
Run simulations to verify the functionality of the cells for both the schematic and layout
views. Use four INVx1 cells as the load for this simulations.
All simulations should use 100ps as their input rise and fall times, all load inverters should be
simulated with schematic views and the circuits being designed in this lab should be simulated
with their extracted views. For the OAI and AOI simulations should be performed with
extracted as well as schematic views.
Report Requirements:
1.
2.
3.
4.
5.
Write a brief, about 1 page summary on how to draw layouts.
Plot the layouts for all the cells that you have designed.
Plot simulation results for each of the cells, to show that they are functionally correct.
Plot the schematic and the simulation schematic views for the OAI and AOI gates.
Create a table that compares the rise and fall times as well as the rising and falling delay
obtained from simulations of the cells using their schematic and layout views.
6. Follow the report writing guidelines about captioning figures, plotting results etc. from lab 2.
7. Submit a single pdf file for your report using submit, the class name is cmpe315_cpatel2 and
the project name is lab3.
THE LABS ARE INDIVIDUAL EFFORTS: INSTANCES OF CHEATING WILL RESULT
IN YOU FAILING THE COURSE.
Principles of VLSI Design
Layout Examples
CMPE 413
Inverter layout alternatives:
1
Layout Examples
Principles of VLSI Design
CMPE 413
Complex Logic Gates
XNOR
A
B
A
B
C
D
Single unbroken line of diffusion not
possible.
“Stacked layout” (on right): signals applied to multiple n- and p-transistors.
Works well for cascaded gates.
2
Layout Examples
Principles of VLSI Design
CMPE 413
Complex Logic Gates
Line of diffusion rule
Transistors form a line of diffusion intersected by poly.
Diffusion will be unbroken if identically labeled Euler paths can be found for the p and n
trees:
C
VDD
D
B
I1
A
I2
Let vertices represent
source/drain connections.
Let edges represent
transistors.
Z
D
I3
I1
Z
A
C
D
I3
B
For example, A-B-C-D works
here (see previous slide).
GND
C
B
I2
A
Z
3
Principles of VLSI Design
Layout Examples
CMPE 413
More Layout Examples
4
Principles of VLSI Design
Layout Examples
CMPE 413
More Layout Examples
5
Principles of VLSI Design
Layout Examples
CMPE 413
More Layout Examples
6
Principles of VLSI Design
Layout Examples
CMPE 413
More Layout Examples
7