Project Task Scheduler

This project will be developed using Verilog on Vivado and executed on the Basys3 board available in thelab. This project is about a system that receives various types of tasks (different types of inputs)and it assigns these tasks to various resources (that we will call stations) within the systemthat are capable of handling the task received. All this is done with a view of utilizing thestations efficiently and finishing the tasks as quickly as possible. I will attach three files which are the most important to follow. I will attach how the grading would be, the instructions for the project and the layout that needs to be filled out. EE 2742 (Fall 2023)—Project: Task Scheduler
EE 2742
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Project: Task Scheduler
Version 1: The outputs for the T = 11 input in the truth table of Figure 5 have been changed to “don’t cares.”
The version number will increase with any changes.
Here are a few points to keep in mind.
• This project is to be done by each student individually. While it is OK to discuss ideas among yourselves,
copying code from another person is not acceptable.
• The project will be developed using Verilog on Vivado and executed on the Basys3 board available in the
lab.
It is recommended that you use Vivado installed on your personal device to work on the project outside
the lab hours.
• You would be able to test parts of your design using the Vivado environment. To test your design on the
Basys3 board, the lab will be open at other times that will be announced separately.
• The project has several layers. Developing a core layer could get you 100% of the points. The additional
layers will give you bonus points. The bonus parts are indicated in blue.
• In addition to demonstrating your project on the Tuesday of the last week of classes (November 28,
2023), you will also have to submit a project report and your Verilog code by midnight on Thursday of
the last week of classes (November 30, 2023).
Details of various elements of the project are posted in a separate file called “Project Guidelines and
Timelines” in the Moodle project folder.
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The Setting
This project is about a system that receives various types of tasks (different types of inputs)
and it assigns these tasks to various resources (that we will call stations) within the system
that are capable of handling the task received. All this is done with a view of utilizing the
stations efficiently and finishing the tasks as quickly as possible.
Within this setting we will see several variations. You will be able to implement the
project at different levels of complexity, with higher complexity implementations receiving
more points.
EE 2742 (Fall 2023)—Project: Task Scheduler
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2
A Simple Scheduler
Consider a system that receives a task (inputed through input lines) and processes the task
at a station, provided the station is free. A task can be of two types, 1, and 2. A task of
type 1 requires 1 clock cycle to complete and a task of type 2 takes 2 clock cycles. That is, if
a task of type 1 is assigned to the station at clock cycle t, then another task can be assigned
to the station at cycle t + 1. On the other hand, if a task of type 2 is assigned to the station
at time t, then it is free to accept a new task only at time t + 2. If the station is unable to
accept the task, the scheduler sets an output f to 1.
Let T be the input indicating the arriving tasks. Here T can take a value of 0, 1, 2, where
0 indicates that there is no task, and 1, 2 indicate the type of the arriving task. That is,
absence of a task is represented as a task of type 0.
The station can be in one of several present states (denoted by S):
• idle: no task running on it,
• type1: a type 1 task running on it,
• type21: a type 2 task running on it for the first clock cycle; recall that a type 2 task
runs for 2 clock cycles, or
• type22: a type 2 task running on it for the second clock cycle.
The next state (S ∗ ) of a machine that implements this system is given by the state table in
Figure 1. The output f is a Mealy output.
Next State S ∗
Present State
Output f
S
T =0
1
2
0
1
2
idle
idle
type1
type21
0
0
0
type1
idle
type1
type21
0
0
0
type21
type22
type22
type22
0
1
1
type22
idle
type1
type21
0
0
0
Figure 1: A state table for the simple scheduler.
Observe that unless the station is in the first clock cycle of a type 2 task, it can accept
a new task. This indicates why f = 1 only in the third row corresponding to state type21.
EE 2742 (Fall 2023)—Project: Task Scheduler
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In the third row, f = 0 for input T = 0 as there is no task to be rejected. From the type21state, the station always goes to state type22. For all states other than type21, a 0 input
takes the machine to idle, a 1 input takes it to type1, and a 2 input takes it to type21.
It is easy to write Verilog code for this. However, observe that we need not distinguish
between states idle, type1, and type22. So just two states, type21, and rest suffice. This
gives us the state table of Figure 2.
Present State
Next State S ∗
Output f
S
T =0
1
2
T = 0 T = 1, 2
type21
rest
rest
rest
0
1
rest
rest
rest type21
0
0
Figure 2: A reduced state table for the simple scheduler.
Nevertheless, you could still write the code for the first larger table, instead of the second
one, and Vivado will typically take care of optimizing the design. However, the smaller code
may be less error prone.
This gives us the structure shown in Figure 3.
Task T
Simple Scheduler
f
clock
Figure 3: Structure of the simple scheduler
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An Second Simple-Scheduler Structure
An alternate way to build the simple scheduler of Section 2 is to make two Verilog modules,
one each for the station and an “allocator.” The allocator module receives two inputs, T
EE 2742 (Fall 2023)—Project: Task Scheduler
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(task) and a ready signal r from the station, if it is ready to receive a new task. The station
receives a task from the allocator and lets it know through r once it has finished with its
current task. The station basically implements the smaller state table of Figure 2 with some
simple changes as shown in Figure 4.
Next State S ∗
Present State
Output
S
A = 0, 1
2
r
type21
rest
rest
0
rest
rest
type21
1
Figure 4: A state table for the station
The Allocator module looks at input T (from outside) and r from the station to produce
outputs f and a (for allocate, that takes value 0, 1, 2, just like T ). The Allocator module
is a combinational circuit with the truth table shown in Figure 5. Here the Allocator sends
T
r
f
a
00 0
0
00
00 1
0
00
01 0
1
00
01 1
0
01
10 0
1
00
10 1
0
10
11 0
x
xx
11 1
x
xx
Figure 5: A truth table for the allocator. An “x” indicates a don’t care as we do not have a
type 3 task.
the value of T to the station (through output a), provided the station is ready. The station
indicates to the Allocator whether it is ready or not, using the variable r.
The Scheduler now has the structure shown in Figure 6.
EE 2742 (Fall 2023)—Project: Task Scheduler
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f
a
Task T
Allocator
r
Station
clock
Simple Scheduler
Figure 6: An alternate structure of the simple scheduler
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Variations to the Simple Scheduler
The structure of the simple scheduler discussed in Sections 2 and 3 can be extended to
accommodate a more general scenario. We explain some of the directions for these extensions
below.
Multiple Task Types: We have discussed a scenario with two task types, 1 and 2, and
used the value 0 to represent “no task.” Suppose you has x task types, 1, 2, · · · , x − 1, x.
Then we can use the values 0, 1, 2, · · · , x − 1, x to represent the task types and the “no task
type.” That is, we need to represent x + 1 values for the incoming task.
If 2b−1 < x + 1 ≤ 2b , the task can be represented with b bits. As an example, Sections 2 and 3 used x = 2, and since 21 < 3 = x + 1 ≤ 22 , it used b = 2 bits to represent each task. Multiple Task Inputs: Suppose y ≥ 1 different tasks can come in to the scheduler at the same time. Let all of these tasks be one of x task types, each of which require b bits (where 2b−1 < x + 1 ≤ 2b ). So the scheduler would now have yb input bits. As an example if x = 2, so b = 2 (see above) and suppose y = 3 (three tasks can come in simultaneoiusly. Here we will use 6 input bits T = T5 T4 T3 T2 T1 T0 . If T = 00 00 00, then there is no task at the input. If T = 10 00 00 or 00 10 00 or 00 00 10, then there is only one type-2 task at the input. If T = 10 01 10, there are three tasks at the input, two of which are type 2 tasks. Input T = 11 00 00 is illegal, unless there is a type 3 task. EE 2742 (Fall 2023)—Project: Task Scheduler 6 Task Handling Time: In Sections 2 and 3 we assumed the tasks of types 1 and 2 took 1 and 2 clock cycles, repectively to handle. A task of type 1, is handled in 1 unit of time, so a station handling this task is free to take up a new task at the next cycle; consequently, its ready line r (see Section 3) does not go to 0, even after it has been assigned a type 1 task. On the other hand a Type 2 task causes the ready line to go to 0 for 1 clock cycle. Consider the case if the type 2 task required 3 units of time. We would now have an additional state in the tables of Figures 2 and 4. The machine would go from state type21 to state type22 on all inputs. State type22 would now behave like state type21 of Figures 2 and 4. In general, if a task requires α clock cycles to process, the station handling the task should go through a sequence of α − 1 states during which r = 0, before it comes to state rest and indicates that it is free for a new task. Multiple Stations: Suppose there are multiple stations that can serve the incoming tasks. Each station can be build as explained in Section 3 and earlier parts of this section. Each station would receive its own task input and produce its own ready output. The stations operate independently and can be designed to have their own processing time for each task type. For example a task of type 1 may be executed in 2 clocks on one stateion and 3 clocks in another. It is also possible for a station to not be able to process a particular type of task. The New Allocator: The Allocator module must now take into account the variations mentioned above. It accepts yb task inputs and, if there are z stations, it also accepts z ready inputs. It outputs z task allocations, one for each station. The entire scheduler now has the form shown in Figure 7. Notice that the Allocator receives yb bits of task inputs, and sends a b-bit task allocation A to each station. It also receives a bit r from each station that indicates the readiness of the station to accept a task. For reasons that will become clearer in the next section, the output of the Allocator can be several bits wide, and that the Allocator itself may be a sequential circuit. The main function of the Allocator, namely to allocate tasks to the stations is simply an extension of the description in Section 3. The allocator takes the following into consideration in allocating tasks. • Tasks must be assigned only to stations that can process them. Not all stations may EE 2742 (Fall 2023)—Project: Task Scheduler 7 F Task T yb Allocator clock b b b A r Station 1 A r Station 2 A r Station z Extended Scheduler Figure 7: Structure of the extended scheduler be able to process all types of tasks. • What is the largest number of tasks that can be accommodated? • What is the largest number of stations that can be occupied? • How can the processing time of tasks be reduced? The Allocator then comes up with an assignment of tasks to stations. 5 The Project The project is an extension of the ideas in the preceding sections. The broad structure of the system to be implemented in the project is shown in Figure 8. The main difference between Figures 7 and 8 are the “Other inputs” and the Display unit. Not shown in these figures are other modes of operation the scheduler must have (these may be useful to develop, debug and demonstrate your work). We explain these aspects below. EE 2742 (Fall 2023)—Project: Task Scheduler 8 Display Unit Task T yb Allocator clock b b Other inputs from stations b A r Station 1 A r Station 2 A r Station z Project Top Module Figure 8: Structure of the extended scheduler 5.1 Modes of Operation The scheduler operates in several modes. We explain some of them here. Section 8 will detail how you can switch between these modes. In all modes the results of the work done by the top module is displayed on the Basys3 board. The first two modes are necessary for you to build. The remaining modes are for bonus credit. Normal Mode: Here the scheduler operates as illustrated earlier, namely receiving tasks and allocating them to the stations. Reset Mode: The scheduler goes to a reset state. In this state, there are no tasks at the input (all tasks are ignored) and all stations are in the idle state. This mode is important to bring your scheduler to a fixed starting point from where you can test its other functionalities. This mode can be synchronous (everything gets reset with the system clock) or asynchronous (things get reset as soon as we set the switches for this mode, see Section 8). Basys3 EE 2742 (Fall 2023)—Project: Task Scheduler 9 Debug Mode: In this mode you can add special features to your project that help you implement the project. One feature of this mode that you are expected to implement is to select a single particular station to work normally and all other stations to not be ready at all. Let the z stations in the system be numbered 0, 1, · · · , z − 1. For example if you indicated in the debug mode that only Station 0 is to be active, then all of stations 1, 2, · · · z − 1 would set their ready lines to 0 and station 0 would work normally. This allows you to test Station 0 separately (in this example). Program Mode: This is explained in Section 7, page 12. Section 7 (page 12) provides a possible additional mode for variable processing times. 5.2 (Other) Inputs Here we describe the inputs your project requires (or could use). Some of the inputs (such as the Tasks using yb bits) have been described before. Clearly there must be inputs indicating the mode of operation. If the debug mode is implemented, you will need inputs to indicate which station you want to keep active. The display unit may employ multiple 7-segment displays. For this you will need the onboard clock of the Basys3 board (as was done in a lab exercise). System Clock: This is the clock used to operate the scheduler in the normal (and possibly other) modes. This clock will be through an externally connected debounced push button switch (you have done this in a lab exercise). It is important that this clock input be debounced. Without a debounced button, your project may produce erroneous results (even if your code was correct). To distinguish this clock from other clocks that you may use (for example for the 7-segment display), we will call the clock described here as the system clock. You will lose points if you do not use an externally connected debounced button here. 5.3 Display Unit The implementatuion of your project needs to be demonstrated. You will have to use the Basys3 LEDs and 7-segment displays for that. The display unit facilitates this. For example EE 2742 (Fall 2023)—Project: Task Scheduler 10 to use multiple 7-segment displays, you willll need a counter that uses the onboard clock (not the pusbutton based system clock). This, for example, would be one of the things in the display unit. 6 Project Requirement (Basic) To receive 100% of the credit for the project, the following must be done correctly. • The scheduler must have the normal and reset modes. • In the normal mode, the scheduler must – Accept two types of tasks (x = 2). – Accept two tasks simultaneously (y = 2). – Serve two stations, numbered 0, 1 (here z = 2). Each station can accept both type of tasks. – The time (number of clock cycles) for each station to serve each type of task is specified in the table of Figure 9. Task Station Type 1 Type 2 0 1 2 1 3 1 Figure 9: Task processing times for the basic implementation. – The project must display a flag f (on an LED) that indicates whether or not the scheduler was able to assign all its tasks in the current clock cycle. – The project must display on a single 7-segment display the total number of tasks assigned since the last reset. The value displayed can be in hexadecimal, so that a maximum of 15 tasks can be shown. If a 16th task is assigned, then the count can go back to 0. – Extra credit can be obtained if you display on two separate 7-segment displays, the count of the tasks allocated to the two stations. EE 2742 (Fall 2023)—Project: Task Scheduler 11 • In the reset mode, the inputs are ignored, the stations are all in the idle state and f flag indicates no unassigned task and the task count displayed is 0. If you are displaying the count on two 7-segment diplays, then they must both be set to 0. 7 Bonus Additions to the Project Here we describe additions to the project described in Section 6 for which you can receive bonus credit. Task Types: The number of tasks types, x can be increased from 2 to 4. x = 3 is not allowed. The part related to the number of stations (see below) provides additional details. Your choice of x = 2 or 4 is independent of the values you select for y and z (see below). Number of Tasks: The number of simultaneously arriving tasks, y, can increase from 2 to 3. Your choice of y is independent of your choice of x and z (see below). Number of Stations: The number of stations, z, can be increased from 2 to 3 or 4. This increase in the number of stations is independent of the values of x, y that you choose to implement. The tables in Figure 10 show the time each station needs for each task. We have separate tables for x = 2 and x = 4. cycles for x = 2 cycles for x = 4 Task Task Station Type 1 Type 2 Station Type 1 Type 2 Type 3 Type 4 0 1 2 0 1 2 3 4 1 3 1 1 2 1 2 3 2 1 1 2 1 1 1 1 3 2 2 3 2 2 – – Figure 10: Task processing times for the bonus implementations. A “–” indicates that the station cannot handle that particular type of task. EE 2742 (Fall 2023)—Project: Task Scheduler 12 If you decide to use z = 3 (three stations), then just ignore the last row of the tables in Figure 10. The extra credit (see portion in blue on page 10) for showing the station information on separate 7-segment displays applies here as well. Notice that the table of Figure 10 for x = 2 is a generalization of the table in Figure 9 the “Basic Implementation” of Section 6. Also notice that the x = 4 table in Figure 10 is a generalization of the x = 2 table of the same figure. Thus, it is possible for you to begin with a basic implementation and then extend it to cover the bonus situations. Program Mode: If you elect to do so, you can also allow your scheduler to program the time taken by each station to process each task. For example, you can set your scheduler to decide that a task of type 1 takes 4 units of time on station 1. This requires the following considerations: • In this mode, you will have to specify a task type (one of x), a station number (one of z) and the number of vlock cycles needed to process the task type on that station. That is, you are allowing your implementation to alter the entries in the above table. • Instead of programming a station to operate as a finite-state machine that keeps track of the number of clock cycles it stays busy, you will need registers to hold the entry of the Table in Figure 10 (or Figure 9). Further there must be a counter that initializes with the contents of the above resgister and count down to 0 to indicate that the task is processed. If this bonus approach is not selected, the countdown to readiness of a station can be baked into the state machine of the station as in Figure 4. 8 Inputs-Outputs, and Constraints File Here we describe input-output layout of the Basys3 board for the different options in the project. These inputs and outputs must be specified through a constraints file. EE 2742 (Fall 2023)—Project: Task Scheduler 13 Recognize that switches, external button, and onboard clock will be used as inputs to your project, where as the LED and 7-segment displays will be used as outputs. The role of the system clock, onboard clock and 7-segment displays have been clarified earlier. Here we detail the uses of the switches and LEDs of the Basys3 board. The leftmost two switches of the Basys3 board are to be used for the mode. In Section 5.1 we described three modes with a possible fourth “Programming Mode” described in Section 7 (page 12). The two switches allow you to represent 4 modes. The following figures show the state of the 16 switches and LEDs available in the Basys3 board. The switches are denoted as , , 2 for the ON, OFF and unknown states, respectively. The corresponding notation for the LEDs is •, •, ◦. number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 z }| { LEDs ◦ ◦ ◦ ◦ ◦ ◦ ◦ ◦ ◦ mode ◦ ◦ ◦ ◦ ◦ ◦ ◦ switches 2 2 2 2 2 2 2 2 2 2 | {z } 2 2 2 2 2 2 mode Use the following assignment of bit strings to modes Switch setting Mode 00 Reset 01 Normal operation 10 Debug 11 Program LEDs 1, 2 are also expected to reflect the mode used currently. We now describe the switch assignments for switches (3 − 16) for the various modes. Reset Mode: Here only the first two switches are used. number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LEDs • • ◦ ◦ ◦ ◦ ◦ ◦ ◦ switches | {z } reset ◦ ◦ ◦ ◦ ◦ ◦ • 2 2 2 2 2 2 2 2 2 2 2 2 2 2 EE 2742 (Fall 2023)—Project: Task Scheduler 14 Normal Operation Mode: Here we need to input the (at most) 3 incoming tasks each with (at most) 4 types. For these 4 types and the “no-task” type (5 possibilities), we need 3 bits. Thus the number of bits needed for 4 tasks is 4 × 3 = 12. The f output is shown in the rightmost LED. The switches and LEDs for the Normal mode have the following form. number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Tasks LEDs • switches • z ◦ ◦ ◦ 2 2 2 | {z } | {z normal Task 1 ◦ ◦ ◦ }| ◦ 2 2 2 2 } | {z Task 2 ◦ ◦ ◦ 2 2 } | 2 ◦ { ◦ ◦ f ◦ 2 2 } 2 2 {z Task 3 If your implementation has fewer than 3 incoming tasks or fewer than 4 task types, then use a subset of the switches in the above layout. Debug Mode: For the debug mode suggested, you need to specify one station (out of at most 4 stations, numbered 0, 1, 2, 3) to be active. This requires two switches (bits). Assign them as shown below. number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 station LEDs • switches • z }| { z ◦ ◦ ◦ Tasks ◦ ◦ 2 2 2 2 2 | {z } | {z } | {z debug station Task 1 }| ◦ ◦ ◦ ◦ 2 2 2 2 } | {z 2 } 2 | 2 ◦ ◦ ◦ Task 2 {z ◦ { ◦ 2 2 } Task 3 In this mode the output f need not be displayed. Program Mode: We well program one station and one Task type at a time. For this mode we need to specify a station (2 bits), a task (3 bits) and the time needed for the task to execute in that station (4 bits); note that the time needed should be ≥ 1, as for a time of t, ready should be set after t − 1 cycles. EE 2742 (Fall 2023)—Project: Task Scheduler number 1 2 3 4 5 station LEDs • switches • 7 z }| { z }| ◦ ◦ ◦ ◦ ◦ station 8 9 10 11 12 13 14 15 16 { ◦ z }| ◦ ◦ ◦ { ◦ ◦ ◦ ◦ ◦ 2 2 2 2 } | {z 2 } 2 2 2 2 Clock cycles Task 2 2 2 2 2 | {z } | {z } | {z prog 9 6 15 Task 1 clock cycles Best Practices The following points may help you successfully implement the project. • Understand the project well and ask about any questions you have • Collaborate with others, but you cannot copy code from others. All your code should use the αβ convention. • Conceptualize the project (possibly in terms of Figure 8. • Build the modules in pieces and put small modules together to create larger ones. Keep the following in mind at each stage. – Check the schematic of the module to see it has the right inputs and outputs. – Use a testbench to test the functionality of the module (this can be done outside the lab). – After you put several modules together, check the schematic again to make sure the structure is correct. There will be points for using testbenches. • In building a module leave room to expand it to an optional part. You can first build the basic part and then add the optional parts as you proceed. EE 2742 (Fall 2023)—Project: Schedule and Grading Template EE 2742 1 Project: Schedule and Grading Template Version 0: The version number will increase as additional details and possibilities are added. Here are a few points to keep in mind. • This project is to be done by each student individually. While it is OK to discuss ideas among yourselves, copying code from another person is not acceptable. • The project is to be developed using Verilog on Vivado and executed on the Basys3 board available in the lab. Vivado is available for free download for Windows. A virtualized environment may have to be used for the Mac and iOS devices. Ii is recommended that you use Vivado installed on your personal device to work on the project outside the lab hours. • You would be able to test parts of your design using the Vivado environment. A schedule will be posted on the Project tab of Moodle. There are three parts to your project, are due on as detailed below. 1. Graded element Weight Date and time due Site Verilog code 25% midnight on November 28, 2023 Moodle 50% various times during the (including constraints and testbench) 2. Project demonstration Lab day on November 28, 2023 3. 1 Project report 25% by midnight on November 30, 2023 Gradescope Verilog Code, Constraints and Testbench You could lose points for deviation from the guidelines given below. • All files (Verilog source, testbench, constraints) must be uploaded to the project portal by midnight on Tuesday, November 28, 2023. The code upload portal will close at midnight. • Each source file (code, testbench, constraints) should begin with a comment line with your name and section number for EE 2742. EE 2742 (Fall 2023)—Project: Schedule and Grading Template 2 • You should use an αβ suffix for all your module names (including in testbench(es)); here αβ denotes the first letters of your first and last name (for me αβ = RV). 2 Project Demonstration In general, it is expected that you will be available for about 75 minutes during your section of the lab; it is anticipated that you will be able to leave before that time is over. You can spend the first 10–15 minutes to ready your project for demonstration (compile your project and load it into the Basys3 board); this time should not be used to work on the project. You cannot do the presentation remotely. We will have a tight schedule and it is important that you all stick to the proposed schedule. Nominally, we will use the following convention for deciding when you need to be at the lab. We will use your Lab 9 team assignment. • If yours is the first number in your team, then you will be expected to be present from the start of your section to about 65 minutes after that. For example in Section 1 that starts at 7:30 am, you will have to be present approximately 7:30–8:35 am. • If yours is the second number in your team, then you will be expected to be present from about 45 minutes from the start of your section to about 65 minutes after that (to the end of your section). For example in Section 2 that starts at 10:30 am, you will have to be present approximately 11:15 am–12:20 pm. You can arrive early if you wish and wait. Whenever possible, we may be able to accommodate you earlier than your designated slot, particularly since some sections have fewer people in them. During your presentation time, you are to present your project to the instructor in about 10 minutes. Since time is short it is essential that you be fully prepared to make your presentation. • Please arrive on time and program your project on the Basys3 board. • One key element of your project is the input/output (using the Basys3 switches, buttons, LEDs and 7-segment display). Without any observable behavior, your EE 2742 (Fall 2023)—Project: Schedule and Grading Template 3 project will receive a 0 for the demonstration. Therefore it is critical that you display your project’s behavior correctly. • During the demonstration, you will be asked to show the functioning of the project under various input conditions. You may also be asked some questions about the implementation of your project. • It is recommended that you write down a mapping of input and output variables to Basys3 elements (switches, buttons, LEDs and 7-segment display), not by their names, but by the positions on the Basys3 board, so that you do not run into delays and difficulties with your demonstration. A template that may help you is posted. 3 Project Report The project report must be submitted in Gradescope by midnight on Thursday, November 30, 2023. • Your report should not exceed 3 pages. • You should include the following in clearly marked sections in the report. – A description of any design choices you made, particularly those you were unable to demonstrate, and your reason for the choice. – You can add any explanation you wish about parts that you could not implement, particularly your thoughts on how you may have approached their implementation, or any difficulties you ran into in implementing them. – Indicate how you used the ideas from labs exercises in your project.