CMPEN 331 – Computer Organization and Design, Lab 3

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     School  of  Electrical  Engineering  and  Computer  Science    
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CMPEN  331  –  Computer  Organization  and  Design,    
Lab  3  
Due  Sunday  November  3  October  27,  2019  at  11:59  pm  (Drop  box  on  Canvas)  
 
This lab introduces the idea of the pipelining technique for building a fast CPU. The students will obtain
experience with the design implementation and testing of the first two stages (Instruction Fetch, Instruction
Decode) of the five-stage pipelined CPU using the Xilinx design package for FPGAs. It is assumed that students
are familiar with the operation of the Xilinx design package for Field Programmable Gate Arrays (FPGAs)
through the Xilinix tutorial available in the class website.
1.   Pipelining
Pipelining is an implementation technique in which multiple instructions are overlapped in execution. The fivestage pipelined CPU allows overlapping execution of multiple instructions. Although an instruction takes five
clock cycle to pass through the pipeline, a new instruction can enter the pipeline during every clock cycle. Under
ideal circumstances, the pipelined CPU can produce a result in every clock cycle. Because in a pipelined CPU
there are multiple operations in each clock cycle, we must save the temporary results in each pipeline stage into
pipeline registers for use in the follow-up stages. We have five stages: IF, ID, EXE, MEM, and WB. The PC can
be considered as the first pipeline register at the beginning of the first stage. We name the other pipeline registers
as IF/ID, ID/EXE, EXE/MEM, and MEM/WB in sequence. In order to understand in depth how the pipelined
CPU works, we will show the circuits that are required in each pipeline stage of a baseline CPU.
2.   Circuits of the Instruction Fetch Stage
The circuit in the IF stage are shown in Figure 2. Also, looking at the first clock cycle in Figure 1(b), the first lw
instruction is being fetched. In the IF stage, there is an instruction memory module and an adder between two
pipeline registers. The left most pipeline register is the PC; it holds 100. In the end of the first cycle (at the rising
edge of clk), the instruction fetched from instruction memory is written into the IF/ID register. Meanwhile, the
output of the adder (PC + 4, the next PC) is written into PC.
3.   Circuits of the Instruction Decode Stage
Referring to Figure 3, in the second cycle, the first instruction entered the ID stage. There are two jobs in the
second cycle: to decode the first instruction in the ID stage, and to fetch the second instruction in the IF stage. The
two instructions are shown on the top of the figures: the first instruction is in the ID stage, and the second
instruction is in the IF stage. The first instruction in the ID stage comes from the IF/ID register. Two operands are
read from the register file (Regfile in the figure) based on rs and rt, although the lw instruction does not use the
operand in the register rt. The immediate (imm) is sign- extended into 32 bits. The regrt signal is used in the ID
stage that selects the destination register number; all others must be written into the ID/EXE register for later use.
At the end of the second cycle, all the data and control signals, except for regrt, in the ID stage are written into the
ID/EXE register. At the same time, the PC and the IF/ID register are also updated.
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     School  of  Electrical  Engineering  and  Computer  Science    
Figure 1 Timing chart comparison between two types of CPUs
Figure 2 Pipeline instruction fetch (IF) stage
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Figure 3 Pipeline instruction decode (ID) stage
4.   Table 1 lists the names and usages of the 32 registers in the register file.
Table 1 MIPS general purpose register
 
$zero
$at
0
1
Constant 0
Reserved for assembler
$v0, $v1
$a0 – $a3
$t0 – $t7
$s0 – $s7
$t8, $t9
$k0, $k1
$gp
$sp
$fp
$ra
2, 3
4–7
8 – 15
16 – 23
24, 25
26, 27
28
29
30
31
Function return values
Function argument values
Temporary (caller saved)
Temporary (callee saved)
Temporary (caller saved)
Reserved for OS Kernel
Pointer to Global Area
Stack Pointer
Frame Pointer
Return Address
 
5.   Table 2 lists some MIPS instructions that will be implemented in our CPU
Table 2 MIPS integration instruction
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6.   Initialize the first 10 words of the Data memory with the following HEX values:
A00000AA
10000011
20000022
30000033
40000044
50000055
60000066
70000077
80000088
90000099
7.   Write a Verilog code that implement the following instructions using the design shown in Figure 2 and Figure 3.
Write a Verilog test bench to verify your code: (You have to show all the signals written into the IF/ID register
and the ID/EXE register in your simulation outputs)
# address
100:
104:
instruction
lw $v0, 00($at)
lw $v1, 04($at)
comment
# $2 ß memory[$1+00]; load x[0]
# $3 ß memory[$1+04]; load x[1]
Assume that the register $at has the value of 0
8.   Write a report that contains the following:
a.   Your Verilog design code. Use:
i.   Device: XC7Z010- CLG400 -1  
b.   Your Verilog® Test Bench design code. Add “`timescale 1ns/1ps” as the first line of your test bench file.
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c.   The waveforms resulting from the verification of your design with simulation showing all the signals
written into the IF/ID register and the ID/EXE register.
d.   The design schematics from the Xilinx synthesis of your design. Do not use any area constraints.
e.   Snapshot of the I/O Planning and
f.   Snapshot of the floor planning
9.   REPORT FORMAT: Free form, but it must be:
g.   One report per student.
h.   Have a cover sheet with identification: Title, Class, Your Name, etc.
i.   Using Microsoft word and it should be uploaded in word format not PDF. If you know LaTex, you should
upload the Tex file in addition to the PDF file.
j.   Double spaced
10.   You have to upload the whole project design file zipped with the word file.
Hey guys,
Here are some hints to help you with Lab 3:
There is a Lab3 Hints video under “Labs.” If the video is not playing with sound, click
Lab3_Hints.mp4 and click “Download Lab3_hints.MP4” and play it on some video player.
1. You should have a module for each of the pieces of the CPU, 9 in total for this lab. I would
recommend having all 9 modules within the same Verilog design source, instead of having each
module in a separate design source. Since future labs will build off of this one, I think it will be
easier to access each module if they’re in the same design source.
2. Initialize all the registers in RegFile to 0.
3. For the Sign Extension module, Review & Verilog_1 slide 60 concatenation will help. The last
example essentially gives you “aaaaab”
4. For the Control Unit, there are good tables in Zybooks 4.4 to help you. The “aluc” output is
going to be the 4-bit output that would come from the ALU control shown in Zybooks.
Essentially, we’re getting rid of the ALU control and incorporating it into the Control Unit. Use
the op and func to help determine what this output should be.
As always, if you have any questions, feel free to email any of the TAs or LAs or come by office
hours.
Best,
Jamie
How to install Vivado WebPACK on a Windows computer
1. First of all, you need a Xilinx account before you can do anything.
a) Go to https://www.xilinx.com and create an account. You can click on the User icon
in the navigation bar and click “Create an account” as shown in the screenshot.
b)
Register the account as you would on any other websites. It would require you to
enter a corporate E-mail. You may use your PSU email account, but any email
account would work for our purpose.
c) You would receive an email tell you to activate the account. Simply click the link in
the email.
d) Don’t forget to sign in into the site after activation.
2. Now you may download the Vivado software. Here is how.
a) Find the “Vivado Design Suite – HLx Editions” in the “Developer Zone” as shown
below:
Alternatively, you may use this link: https://www.xilinx.com/products/designtools/vivado.html
b)
Click on the first option – “Download Vivado Design Suite – HLx Editions”.
c)
As the date I am writing this, the latest version they are offering is 2018.2. In the
page you may find many downloads. Please find the item that says “Full Product
Download” rather than “Update”
d)
Scroll down you can find a download called “Vivado HLx 2018.2: WebPACK and
Editions – Windows Self Extracting Web Installer “, click on that. (If you are
downloading a newer version, download the installer accordingly).
Alternatively, you may use this link for 2018.2:
https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_Vivado
_SDK_Web_2018.2_0614_1954_Win64.exe
e) You would be asked to enter many information in order to download the software.
Click ‘Next’ after you have finished answering these questions. I used ‘Penn State
University’ as my company, but it’s your choice what to enter.
f) Your file should start downloading.
3. Installing the Vivado
a) Run the file you have just downloaded. It would take a while before you see the
main install wizard. Please wait patiently. You should see this window pop up
eventually (it is not that long, usually from 10 secs to 1 minute).
b)
c)
d)
e)
f)
g)
h)
In the following step, you would be asked to enter the User ID and Password. Use
the account you have registered in Step 1.
Read the license and choose ‘I Agree’. If you do not agree to the license of this
software, you may need to drop this course.
Be sure to select Vivado HL WebPACK version! This is the free version, means you
do not need to pay to use this software. It has limited function but should be
sufficient for this course.
Under module selection, default choices are fine. You may uncheck SDK, UltraScale,
UltraScale+ support to save some disk space, they would not likely be used in this
course. But surely you can install them.
Note it would take a huge amount of disk space. You may change the path where it
will install to in this step. If there is no enough space left on the disk, you would have
to make some room for it.
Wait for it to install. Depending on your Internet connection quality, it may take
anything from 5 minutes to infinity.
You are done.
4. If and only if you are trying to install Vivado HL WebPACK 2015 or earlier, or ISE WebPACK,
you would need to obtain and install the WebPACK license manually. Note again: This
step is NOT required for latest version of Vivado.
a) Go to https://www.xilinx.com/support/licensing_solution_center.html
You may be asked to enter some information just like in Step 2.
b) Select the license you would like to generate. Click generate Node-Locked License.
c)
After that, click the Manage Licenses in the same page. Select the License you have
just created, click the download button.
d)
Find and open Manage Xilinx Licenses in the start menu. Use ‘Load License’ to install
the license. Similar things can be also done in ISE.