SQU Programming Research Survey Report

MODULAR PROGRAMMECOURSEWORK ASSESSMENT SPECIFICATION
Module Details
Module Learning Outcomes
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Apply fundamental principles of combinatorial digital logic to expose the
principal building blocks of computer systems –MO2
Understand some of the technical principles and practical details of computer
Networking-MO8
Conduct research into the impact on society of decisions related to sustainability,
e.g. decisions on power consumption by computing devices-MO9
Write programs using assembler- MO6
Use numeric and character data typing and convert between them MO7
Deliverables
Report in Pdf/Doc + Source code + link to demonstration recoding of 10 minutes
PROGRAMMING ASSIGNMENT WITH REPORT (Re-sit)
COMPUTER AND NETWORK SYSTEMS (UFCF93-30-1)
This assignment is divided into two tasks. Tasks1 is a research survey report where as Task2 is
related to programming. The tasks are described as follows:
1. Write a report on the sustainability in the IT industry or how IT can be used to make
other industries or life in general more sustainable. The report should be of 800 words,
and it should use UWE Harvard referencing.
[Marks 40]
2. Adder circuits play key role in the computations. A logical circuit for a half adder
performs addition on single bits. It produces two bits a sum (S) and a carry(C). The
circuit and the truth table can be given in the Figure 1(a) and Figure 1(b) respectively.
(a)
Input
Pins
Output Pins
A
B
Sum
(S)
Carry
(C)
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
(b)
Figure 1 (a) Illustration of logic circuit (b) Truth table for half Adder
Similarly, a full adder is a digital circuit that adds three single bits. It takes two input pins A, B
along with a carry-in (Cin) from previous stage. It has the similar output pins Sum (S) and Carryout (Cout). It can be constructed by the combination of two half adders as shown in Figure 2
Input Pins
Output
Pins
A
B
Cin
S
Cout
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
(a)
Figure 2 (a) Illustration of logic circuit (b) Truth table for 1-bit Full Adder
(b)
In similar manner 4-bit adder can be designed by the combination of 1-bit full adders.
Considering the above discussing about adders, perform the following sub-tasks:
a. Design 4-bit combinational adder and subtracter and simulate it using C
[Marks 20]
b. Design 1-bit adder using flip-flops by using the concepts of finite state machine (FSM).
[Marks 15]
c. Design FSM for 8-bit adder using sequential flip-flops and simulate it Using C.
[Marks 25]
Resources
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C/C++ programming, Microsoft Word
Google Scholar (scholar.google.com)
IEEE Xplore (ieeexplore.ieee.org)
Deliverables
The report and the coding tasks along with the required description must placed into a .zip file
and the hard copy should be submitted
Marking Scheme
1. For Task1 every student is required to produce a report that must be different from others. It
should show a thorough study of high quality research journals and conferences. The marks
will be awarded for:
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Understanding the subject
Proper use of headings and sub-headings in the structure
Correct Terminology
It should be phrased in third person
References (must be peer reviewed journals and conferences)
Citations
Marks [0 -40]
2. Task 2 has 60 marks and these are distributed in the following table.
Po Averag Excellen Marks
Sub-Task Task Evaluation
t
30%
No.
[0-20]
a.
C code (Efficient logic, use of loops and or e
conditional statements) and testing
c.
Construction of Adder using flip-flops,
need to use finite state machine
[0-15]
d.
I.
8-bit adder design, FSM table and
diagram,
[0-15]
II.
C code (Efficient logic, use of loops
and conditional statements) and
testing
[0-10]