Computer Organization and Assembly Language Programming

ECE 375

Computer Organization and Assembly Language Programming

Winter 2018
Assignment #2

[25 pts]

1- Consider the internal structure of the pseudo-CPU discussed in class augmented with a single-port register file

(i.e., only one register value can be read in a cycle) containing 32 8-bit registers (R0-R31) and a carry bit (C-
bit), which is set/reset after each arithmetic operation. Suppose the pseudo-CPU can be used to implement
the AVR instruction ADIW ZH:ZL,32 (Add immediate to word). ADIW is a 16-bit instruction, where the upper
byte represents the opcode and the lower byte represents an immediate value, i.e., “32” (do not worry about
the fact that the actual format is slightly different). Give the sequence of microoperations required to Fetch
and Execute the ADIW instruction. Your solutions should result in exactly 5 cycles for the fetch cycle and 6
cycles for the execute cycle. Assume the memory is organized into addressable bytes (i.e., each memory
word is a byte), MDR, IR, and AC registers are 8-bit wide, and PC and MAR registers are 16-bit wide. Also,
assume Internal Data Bus is 16-bit wide and thus can handle 8-bit or 16-bit (as well as portion of 8-bit or 16-
bit) transfers in one microoperation and only PC and AC have the capability to increment itself.

[25 pts]
2- Consider the internal structure of the pseudo-CPU discussed in class augmented with a single-port register file

(i.e., only one register value can be read at a time) containing 32 8-bit registers (R31-R0) and a Stack Pointer
(SP). Suppose the pseudo-CPU can be used to implement the AVR instruction ICALL (Indirect Call to
Subroutine) with the format shown below:

ICALL pushes the return address onto the stack and jumps to the 16-bit target address contained in the Z
register. Give the sequence of microoperations required to Fetch and Execute AVR’s ICALL instruction.
Your solutions should result in exactly 6 cycles for the fetch cycle and 8 cycles for the execute cycle. Assume
the memory is organized into addressable bytes (i.e., each memory word is a byte), MDR is 8 bits, and AC,
SP, PC, IR, and MAR are 16 bits. Also, assume Internal Data Bus is 16-bit wide and thus can handle 8-bit or
16-bit (as well as portion of 8-bit or 16-bit) transfers in one microoperation and SP has the capability to
increment/decrement itself. Clearly state any other assumptions made.

ALU$

…

To/from memory
and I/O devices

Internal
control
signals

External
Control signals

Internal Data Bus

…

AC$

IR$ PC$ MDR$ MAR$

CU$

Register$File$
R31$–$R0$

C

+1$

1001 0101 0000 1001

[25 pts]
3- Suppose the following array of numbers are stored in the Data Memory (represented in hexadecimal):

Address Content
0100: 01 

0101: BE 

0102: 35 

0103: EC 

0104: 48 

0105: 2D 

0106: 04 

0107: 02

(a) Assuming these numbers are signed numbers, write a subroutine using AVR assembly that (1) determines
the smallest number among the 8 numbers stored in memory and (2) stores that number in the memory
location $0108. Clearly comment and explain your code. Use the skeleton code shown below to
implement your subroutine:

.ORG 0x0046
…Initialize stack…

RCALL MIN
…
…

.ORG 0x0060
MIN:

… ; Your code goes here
… ;
RET

.DSEG

.ORG 0x0100
DATA: .BYTE 8
RESULT: .BYTE 1

(b) Suppose these numbers are unsigned numbers (i.e., they are positive numbers). Show and explain how
the code developed in part (a) would have to be modified.

[25 pts]
ALU$
…

To/from memory and
I/O devices

Internal
control
signals
External
Control signals
Internal Data Bus

…

AC$
IR$ PC$ MDR$ MAR$
CU$
Register$File$
R31$–$R0$

SP$

+1$

4- Determine the location (i.e., address) and binary code for each instruction in the code developed for Problem
#3 part (a). Clearly explain your answers. Examples of addresses and machines codes for RCALL and RET are
shown below:

Address Binary

.ORG 0x0046
RCALL MIN 0046: 1101 0000 0001 1001
… …
… …

.ORG 0x0060
MIN: …
…

RET ????: 1001 0101 0000 1000